freescale qoriq? communications platforms are the next-generation evolution of our leading powerquicc ? communications processors. built u sing high-performance power architecture ? cores, qoriq platforms enable a new era of networking innovation where the reliability, security and quality of service for every connection matters. qoriq p4080 multicore processor the qoriq p4080 multicore processor, the first product offered in the qoriq p4 platform series, delivers industry-leading performance in the under 30-watt power category. it combines eight power architecture e500mc cores operating at frequencies up to 1.5 ghz with high-performance datapath acceleration logic, as well as networking i/o and other peripheral bus interfaces. the p4080, built in 45 nm technology, is designed to deliver high-performance, next-generation networking services in a very low power envelope. the qoriq p4080 processor is designed for combined control and dataplane processing, enabling high-performance layers 2C7 processing. its high level of integration offers significant performance benefits compared to multiple discrete devices, while also greatly simplifying board design. the processor is well-suited for applications that are highly compute-intensive, i/o-intensive or both. this makes it ideal for applications such as enterprise and service provider routers, switches, media gateways, base station controllers, radio network controllers (rncs), access gateways for long term evolution (lte) and general-purpose embedded computing systems in the networking, telecom, industrial, aerospace and defense markets. key features freescale delivers a groundbreaking three- tiered cache hierarchy on the qoriq p4 platform. each core has an integrated level 1 (l1) cache as well as a dedicated level 2 (l2) backside cache that can significantly improve performance. finally, a multi-megabyte level 3 (l3) cache is also provided for those tasks for which a shared cache is desirable. the corenet? coherency fabric is a key design component of the qoriq p4 platform. it manages full coherency of the caches and provides scalable on-chip, point-to-point connectivity supporting concurrent traffic to and from multiple resources connected to the fabric, eliminating single-point bottlenecks for non-competing resourc es. this eliminates bus contention and latency issues associated with scaling shared bus/shared memory architectures that are common in other multicore approaches. qoriq? communications platforms p4 series p4080 multicore processor buffer manager queue manager core acceleration interface ddr2/ddr3 sdram controller ddr2/ddr3 sdram controller 2 x duart, 4 x i 2 c, interrupt control, gpio, sd/mmc, spi, 2 x usb 2.0/ulpi encryption regex pattern matching engine enhanced local bus controller (elbc) 128 kb backside l2 cache 32 kb l1 i-cache power architecture ? e500mc core 32 kb l1 d-cache corenet? coherency fabric 2 x 4-ch. dma 2 x 4-ch. dma 3 x pci express ? on-chip network on-chip network 2 x serial rapidio ? 18-lane serdes rapidio message unit (rmu) frame manager 4 x 1 gbps ethernet 1 x 10 gbps ethernet real-time debug frame manager 4 x 1 gbps ethernet 1 x 10 gbps ethernet qoriq? p4080 block diagram 1024 kb frontside l3 cache 1024 kb frontside l3 cache
freescale, qoriq, corenet and the freescale logo are trademarks or registered trademarks of freescale semiconductor, inc. in the u.s. and other countries. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? freescale semiconductor, inc. 2008. document number: qp4080fs rev 1 the qoriq p4080 multicore processor is extremely flexible and can be configured to meet many system application needs. the processors e500mc cores, leveraging advanced virtualization technology, can work as eight symmetric multiprocessing (smp) cores, or eight completely asymmetric multiprocessing (amp) cores, or they can be operated with varying degrees of independence with a combination of smp and amp groupings. full processor independence, including the ability to independently boot and reset each e500mc core, is a defining characteristic of the device. the ability of the cores to run different operating systems (oses), or run os-less, provides the user with significant flexibility in partitioning between control, datapath and applications processing. it also simplifies consolidation of functions previously spread across multiple discrete processors onto a single device. advanced virtualization technology brings a new level of hardware partitioning through an embedded hypervisor that allows system developers to ensure software running on any cpu only accesses the resources (memory, peripherals, etc.) that it is explicitly authorized to access. the embedded hypervisor enables safe and autonomous operation of multiple individual operating systems, allowing them to share system resources, including processor cores, memory and other on-chip functions. ecosystem and developer environment developers creating solutions with power architecture technology have long benefited from a vibrant support ecosystem, including high-quality tools, oses and network protocol stacks. freescale has collaborated with our partners on the qoriq p4080 processor to continue our strong ecosystem heritage. this helps to ensure that the best enablement tools are available to cost-effectively meet the unique development challenges of multicore architectures and speed your time to market. to this end, freescale has partnered with virtutech to offer a robust, innovative hybrid simulation environment that provides a controlled, deterministic and fully reversible environment for the development, debugging and benchmarking of software for complex multicore-based architectures. the hybrid simulator combines virtutechs fast, functional simics? model, with a detailed performance model of the platform. this combination enables fast hardware concept testing and evaluation, as well as performance verification and helps accelerate your development cycle, provide more flexible debug capability and improve the overall quality of your software. freescale has also engineered capabilities into the qoriq p4080 to enable advanced debugging while working in tandem with its ecosystem partners to assure availability of tools that can take advantage of these features. these capabilities include integrated instruction trace, watchpoint triggers, cross- event triggers, performance monitoring and other debug features as defined by the power ? isa. these features enable dynamic debug essential for providing visibility into complex interactions that may occur among tasks running on different cores. qoriq p4080 technical specifications ? eight high-performance power architecture e500mc cores, each with a 32 kb instruction and data l1 cache and a private 128 kb l2 cache three levels of instruction: user, supervisor and hypervisor independent boot and reset secure boot capability ? 2 mb shared l3 corenet platform cache ? hierarchical interconnect fabric corenet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst corenet end-points 800 gbps coherent read bandwidth queue manager fabric supporting packet- level queue management and quality of service scheduling ? two 64-bit ddr2/ddr3 sdram memory controllers with ecc and interleaving support ? datapath acceleration architecture incorporating acceleration for the following functions: packet parsing, classification and distribution queue management for scheduling, packet sequencing and congestion management hardware buffer management for buffer allocation and de-allocation cryptographic security acceleration (sec 4.0) regex pattern matching (pme 2.0) ? ethernet interfaces two 10 gbps ethernet (xaui) controllers eight 1 gbps ethernet (sgmii) controllers ? high-speed peripheral interfaces three pci express ? v2.0 controllers/ports running at up to 5 ghz two serial rapidio ? 1.2 controllers/ports running at up to 3.125 ghz ? additional peripheral interfaces two usb controllers with ulpi interface to external phy sd/mmc spi controller four i 2 c controllers two dual uarts enhanced local bus controller (elbc) ? multicore programmable interrupt controller (pic) ? two 4-channel dma engines for more information about virtutech simics, please visit www.virtutech.com . learn more: for current information about freescale products and documentation, please visit www.freescale.com/multicore .
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